Compact semiconductor structure and method for producing the same

ABSTRACT

The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips ( 7, 8 ) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer ( 1 ) of a predetermined thickness consisting of a first insulation material and a second insulation layer ( 10 ) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer ( 1 ). The two or more metallic conductor strips ( 7, 8 ) extend from the first insulation layer ( 1 ) into the second insulation layer ( 10 ) and the second insulation material has a lower relative dielectric constant than the first insulation material.

[0001] The invention relates to a densely packed semiconductor structureand a method for fabricating such a semiconductor structure. Inparticular, the invention relates to a semiconductor structure having aninsulator layer on a semiconductor substrate and also at least twometallic interconnects in the insulator layer. The method forfabricating such a semiconductor structure using “damascene technology”comprises the following steps: production of an insulator layer made ofa first insulator material on a semiconductor substrate. Definition ofregions in the insulator layer made of the first insulator material inwhich trenches are produced, etching of trenches in the insulator layermade of the first insulator material, production of at least twometallic interconnects by metallization of the insulator layer made ofthe first insulator material, so that the trenches are filled withmetal, and polishing of the semiconductor structure, so that themetallization on the surface of the insulator layer made of the firstinsulator material is removed.

[0002] A physical limit is imposed on the “shrinking” of suchsemiconductor structures, i.e. the scaling down of the structure widthand the minimum distances between the interconnects. With ever smallerstructure widths, the electrical coupling of two tracks running parallelincreases drastically. This undesirable parasitic effect leads fromperformance losses through to functionality failures. In particular, acapacitive coupling between word and bit lines or between two adjacentword lines and thus a signal loss may occur. Even in existing DRAMgenerations, both effects lead to losses in the circuit speed or tofunctionality failures (e.g. BLC: Bit Line Coupling).

[0003] To date, coupling effects of this type have been compensated forby adapting the design of the semiconductor structure, e.g. by designingthe word and bit lines to be shorter. However, this is ultimatelyconnected with a higher area requirement.

[0004] It is an object of the invention to reduce the capacitivecoupling between adjacent metallic interconnects of a semiconductorstructure and thus to make it possible to fabricate a more denselypacked semiconductor structure.

[0005] This object is achieved according to the invention by means of asemiconductor structure according to claim 1, and a method forfabricating such a semiconductor structure according to claim 4. Thesubclaims relate to preferred embodiments of the invention.

[0006] SiO₂, which has hitherto been used as a dielectric (intermetaldielectric, IMD), has a relative permittivity of ∈=3.9, so thatcapacitive coupling effects become perceptible below a certain distancebetween adjacent interconnects. This capacitive coupling could bereduced by using novel materials as IMD with a lower relativepermittivity (so-called low-k materials) with an ∈<3.9. However, sincethe low-k materials that are known nowadays are generally stable only upto temperatures of 450° C., the dielectric (the M0 plane) cannot beproduced with this material from the outset because, after theproduction of the dielectric, one or more heat treatment steps(annealing) are necessary, in a manner governed by the overall process,at relatively high temperatures: the heat treatment, e.g. after animplantation (implant annealing), takes place at 960° C., and the heattreatment after e.g. the metallization takes place at 800° C.

[0007] It is only by subsequently etching back the SiO₂ that it becomespossible to fabricate the dielectric between metallic interconnects inthe M0 plane from a low-k material. The filling properties of the low-kmaterial are exploited in this case.

[0008] The semiconductor structure according to the invention ischaracterized in that the insulator layer comprises a first insulatorlayer of predetermined thickness made of a first insulator material, anda second insulator layer of predetermined thickness made of a secondinsulator material, which is arranged above the first insulator layer,the at least two metallic interconnects extending from the firstinsulator layer into the second insulator layer, and the secondinsulator material has a lower relative permittivity than the firstinsulator material.

[0009] Accordingly, the method for fabricating such a semiconductorstructure comprises the etching-back of the first insulator layerbetween the interconnects, so that the at least two metallicinterconnects project above adjacent regions of the first insulatorlayer, and the production of a second insulator layer made of a secondinsulator material on the semiconductor structure, so that the at leasttwo metallic interconnects extend from the first insulator layer intothe second insulator layer, the second insulator material having a lowerrelative permittivity than the first insulator material.

[0010] In a preferred embodiment of the invention, the lower insulatorlayer comprises SiO₂ with a relative permittivity of 3.9; the relativepermittivity of the upper insulator layer is, in particular, less than3.9.

[0011] One advantage of the invention is that only an (etching) stepwhich is simple to control additionally has to be performed, but for therest the method is not significantly more complicated than the methodaccording to the prior art.

[0012] Further features and advantages of the invention emerge from thefollowing description of a preferred embodiment, in which reference ismade to the accompanying drawings.

[0013]FIGS. 1A to F each diagrammatically show the cross section througha semiconductor structure during the individual steps of a contactconnection or during the fabrication of interconnects by means of the“damascene technology”.

[0014]FIGS. 2A and B each diagrammatically show the cross sectionthrough a semiconductor structure with two metallic interconnectsaccording to the prior art.

[0015]FIGS. 3A to C each diagrammatically show the cross section througha semiconductor structure according to the invention with two metallicinterconnects.

[0016] Metallic interconnects of an integrated circuit are preferablyfabricated by means of a damascene method. In the damascene method,firstly the intermetal dielectric (IMD) is applied, and then trenchesare etched into the IMD. In the case of Si semiconductor substrates, theIMD is preferably obtained by means of suitable CVD deposition. Thetrenches are filled with metal by the metal being deposited over thewhole area on the semiconductor substrate and then being removed againfrom the elevated regions of the IMD by means of CMP or etching-back.

[0017]FIGS. 1A to F diagrammatically illustrate the individual steps ofa typical dual damascene method. FIG. 1A illustrates an insulator layer1 (grey area), in which a (contact) opening 2 for a connection to thesemiconductor (not illustrated) situated underneath is provided. Afterthe fabrication of the opening by etching, the semiconductor structureis subjected to heat treatment by heat supply 3 (FIG. 1B). This“annealing step” takes place at a temperature of 800 to 960° C.Afterward, a mask 4 is produced lithographically on the semiconductorstructure, which mask defines the regions in which trenches or furtheropenings are etched (M0 lithography step in FIG. 1C). The etching yieldsthe trenches 5 or expanded openings 2 within the mask windows 4 as shownin FIG. 1D. Afterward, the mask 4 is removed and the semiconductorstructure is metallized, i.e. completely covered with metal (tungsten).Only the metal in the trenches 5 or in the contact windows 2 isrequired, however. The excess metal is removed again by chemicalmechanical polishing (CMP), this finally resulting in the semiconductorstructure with two metallic interconnects 7 and 8 according to FIG. 1F.

[0018] For the fabrication of the semiconductor structure according toFIG. 2A, two interconnects were produced in the insulator layer in themanner described with reference to FIG. 1. To that end, a firstinsulator layer 1 made of a first insulator material was produced on asemiconductor substrate (not illustrated), windows in which trenches 5are produced were defined in the first insulator layer, the trenches 5were etched in the first insulator layer 1, the two metallicinterconnects 7 and 8 were produced in the trenches 5 by metallizationof the semiconductor structure, so that the trenches 5 in the firstinsulator layer 1 are filled with metal 6, and the semiconductorstructure was polished, so that the metallization 6 is removed on thesurface of the first insulator layer 1 and the metal 6 remainsessentially only in the trenches 5.

[0019] The resulting semiconductor structure comprises an insulatorlayer 1 on a semiconductor substrate (not illustrated) and at least twometallic interconnects 7 and 8 in the insulator layer 1.

[0020]FIG. 2B illustrates the semiconductor structure after thedeposition of a covering second layer of the first insulator material 9,the first and second layers of the first insulator material beingseparated by a dashed line for illustration purposes. However, the lowerinsulator layer 1 and the upper insulator layer 9 are generallyessentially homogeneous. A double arrow between the upper edges of thetwo interconnects 7 and 8 indicates the mutual capacitive coupling. Thiscoupling prevents the interconnects 7 and 8 from being packed moredensely, since, below a specific distance between the interconnects, itleads to disturbances in the signals on one or both of theinterconnects.

[0021] In order nevertheless to enable a higher packing denisity thanaccording to this prior art, according to the invention the method ismodified as illustrated in FIGS. 3A to C.

[0022] After the completion of the structure in FIG. 3A (it isequivalent to the semiconductor structure in FIG. 2A), before theapplication of a second insulator layer for the covering of thesemiconductor structure, the first insulator layer 1 is etched backselectively, i.e. the insulator layer 1 is removed only between thetrenches 5; the metallic interconnects 7 and 8 are not significantlyaffected by the etching. As soon as the first insulator layer 1 has onlya predetermined thickness and the at least two metallic interconnects 7and 8 project above their adjacent regions of the first insulator layer1 (FIG. 3B), a second insulator layer 10 made of a second insulatormaterial is produced on the semiconductor structure. As a result, the atleast two metallic interconnects 7 and 8 are embedded in the secondinsulator layer 10 made of the second insulator material in their upperpart. In other words, the interconnects in the first insulator layer 1extend from the first insulator layer 1 into the second insulator layer10. The second insulator layer 10 is illustrated in hatched fashion inFIG. 3C.

[0023] In order to reduce the capacitive coupling between the twointerconnects 7 and 8, a material having a lower relative permittivitythan the first insulator material is chosen as the second insulatormaterial. In particular, a material is chosen which has a relativepermittivity of less than 3.9, compared with 3.9 in the case of SiO₂.

[0024] In a manner similar to the semiconductor structure according toFIG. 2B, the resulting semiconductor structure according to FIG. 3Ccomprises a first insulator layer on a semiconductor substrate (notillustrated) and at least two metallic interconnects 7, o in theinsulator layer. A second insulator layer 10 (hatched area) ofpredetermined thickness is arranged above the first insulator layer 1.In contrast to the prior art, however, in the case of the semiconductorstructure according to the invention, only the first insulator layer 1(grey area) of predetermined thickness is made of a first insulatormaterial, while the second insulator layer 10 comprises a secondinsulator material having a lower relative permittivity than the firstinsulator material, namely preferably a relative permittivity which isless than 3. Furthermore, unlike in the prior art, the two metallicinterconnects 7 and 8 extend from the first insulator layer 1 into thesecond insulator layer 10.

[0025] It must be a further property of the second insulator material,besides that for a low relative permittivity, that voids or shrink holesin the intermetal dielectric layer, which may arise e.g. on account ofoverhanging metal 1 sidewalls, can be avoided during the production ofthe second insulator layer 10. What are appropriate for this purpose arefilling (gap-filled) materials which are currently being developed (inparticular in the case of embedded DRAM elements) and with which evenvery small cavities can be filled very well.

[0026] The surface of the semiconductor structure is finally polished,so that it is finally essentially planar.

List of Reference Symbols

[0027]1 First layer of a first (SiO₂) insulator material

[0028]2 Continuous opening in insulator layer

[0029]3 Heat supply

[0030]4 Exposure mask on insulator layer

[0031]5 Expanded continuous opening/trench

[0032]6 Metal

[0033]7 First metallic interconnect

[0034]8 Second metallic interconnect

[0035]9 Second layer of a first (SiO₂) insulator material

[0036]10 Layer of a second (low-k) insulator material

1. A semiconductor structure comprising: an insulator layer on asemiconductor substrate and at least two metallic interconnects (7, 8)in the insulator layer, characterised in that the insulator layercomprises a first insulator layer (1) of predetermined thickness made ofa first insulator material, and a second insulator layer (10) ofpredetermined thickness made of a second insulator material, which isarranged above the first insulator layer (1), the at least two metallicinterconnects (7, 8) extending from the first insulator layer (1) intothe second insulator layer (10), and the second insulator material has alower relative permittivity than the first insulator material.
 2. Thesemiconductor structure as claimed in claim 1, characterised in that thefirst insulator layer (1) is SiO₂.
 3. The semiconductor structure asclaimed in claim 1, characterised in that the relative permittivity ofthe second insulator layer (10) is less than 3.9.
 4. A method forfabricating a semiconductor structure having an insulator layer on asemiconductor substrate and at least two metallic interconnects (7, 8)in the insulator layer, having the following steps: a) production of afirst insulator layer (1) made of a first insulator material on asemiconductor substrate, b) definition of regions in the first insulatorlayer (1) in which trenches (5) are produced, c) etching of trenches (5)in the first insulator layer (1), d) production of at least two metallicinterconnects (7, 8) in the trenches (5) by metallization of thesemiconductor structure, so that the trenches (5) in the first insulatorlayer (1) are filled with metal, e) polishing of the semiconductorstructure, so that the metallization (6) on the surface of the firstinsulator layer (1) is removed and essentially only metal (6) in thetrenches (5) remains, characterised by the subsequent steps: f)etching-back of the first insulator layer (1) between the at least twometallic interconnects (7, 8), so that the at least two metallicinterconnects (7, 8) project above adjacent regions of the firstinsulator layer (1), g) production of a second insulator layer (10) madeof a second insulator material on the semiconductor structure, so thatthe at least two metallic interconnects (7, 8) extend from the firstinsulator layer (1) into the second insulator layer (10), the secondinsulator material having a lower relative permittivity than the firstinsulator material.
 5. The method as claimed in claim 4, characterisedin that the production of the insulator layer (1) comprises theapplication of an oxide by means of a suitable CVD method.
 6. The methodas claimed in claim 4 or 5, characterized in that the relativepermittivity of the upper insulator layer (10) is less than 3.9.